1. Field of the Invention
The present invention is related to interface devices, and in particular to an interface device which performs an interface function between a high-speed bus and a low-speed bus.
2. Discussion of the Related Art
Deep sub-micron (DSM) process geometries, and in particular DSM system on chip (SOC) designs, represent the current state of the art in chip design. With SOC designs, an entire system is implemented on one chip. Accordingly, many elements of the system share a bus architecture. Performance of the system is dependant upon efficient use of the shared bus. In the case of SOC designs, there are several widely used interface methods, such as PCI (peripheral component interface), 32-bit PC card (referred to as CardBus), and PCMCIA (Personal Computer Memory Card International Association). Regarding operational speed and data transfer efficiency, the PCI and PC card have superior performance as compared with the PCMCIA.
However, as compared with the PCMCIA, the PCI and 32-bit PC card have complex circuits and communication protocols. For small SOC chips, the PCI and 32-bit PC card are inappropriate for interfacing with a host because their size. That is, since the PCI and 32-bit PC card are intended to transmit 32-bit data, they are inappropriate to a host system for transmitting only 8-bit or 16-bit data, considering circuit area and complexity. On the other hand, since the communication protocol of the PCMCIA is relatively simple and its size is small, the PCMCIA is appropriate for a host system that transmits 8-bit or 16-bit data. For this reason, PCMCIA has been widely used in mobile applications. PCMCIA is a PC card for interfacing with a host by an 8-bit/16-bit unit and is mainly used as a memory interface.
PCMCIA, as described above, has advantages such as a small size, a simple communication protocol, and a mobile application. However, many systems have a 32-bit or wider data width bus architecture and use a clock speed greater than that of PCMCIA. Systems or SOCs having a 32-bit bus architecture include a plurality of masters. One of the masters is PCMCIA.
In a 32-bit bus system, PCMCIA can transmit 16-bit data. That is, PCMCIA uses half a bus of the 32-bit bus system. In a case where the PCMCIA operates as a master in the 32-bit bus system, the performance of an entire system decreases. The reason is because when a 16-bit PCMCIA uses a 32-bit bus, the availability of the bus to 32-bit masters is reduced.
As described above, PCMCIA only transmits 16-bit data. When interfacing with another block connected to a shared bus of the SOC by the 32-bit unit, the PCMCIA must request and use the shared bus two times. Furthermore, when interfacing with another block connected to a shared bus of the SOC by the 8-bit unit, the PCMCIA must request and use the shared bus four times. Therefore, as the frequency with which the PCMCIA uses a shared bus increases, the chances that other high-speed masters can use the bus are reduced in proportion to a bus occupation frequency of the PCMCIA.
Bus contention becomes more serious as the clock speed of shared busses increase. Furthermore, where a main object of the PCMCIA is to receive data from a host and access an external memory, since a speed of the external memory is very slow, a time when the PCMCIA occupies a shared bus becomes longer.